Ferroelectric memories have the potential to be developed into nonvolatile memories due to their inherent high performance, such as short write time and high write durability. The memory cell structures in a DRAM can include ferroelectric capacitors and MOS transistors, enabling the stable operation of the memory. Such memory cell structure is disclosed, for example, in IEEE J. Solid-State Circuits, vol. 23, pp. 1171-1175, December, 1989, entitled "An Experimental 512-bit Nonvolatile Memory with Ferroelectric Storage Cell."
The write time of a ferroelectric memory is at least one order of magnitude shorter than that of a flash memory, but is a little longer than that of a non-ferroelectric DRAM. This is due to the fact that the ferroelectric memory has a plate line driven by pulses, though it shows read/write operations similar to those of DRAM. The write durability of a ferroelectric memory is a few orders of magnitude longer than that of a flash memory, but a few orders of magnitude shorter than that of non-ferroelectric DRAM. The write durability is limited by the fatigue of the ferroelectric capacitor caused by polarization switching for its write operations.
A ferroelectric memory has the disadvantage of low density, which results in the following problems for such a DRAM cell structure. The plate must be separated into pulsed plate lines, and a 2T/2C (two-transistor and two-capacitor) cell must be employed instead of a 1T/1C (one-transistor and one-capacitor) cell in order to cope with the generation of a reference voltage in the complementary bit lines. Also, the signal reduction should be considered according to fatigue.
The pulsed plate lines also result in an increase in the active power consumption. In order to reduce this power consumption, a multi-divided plate-line architecture for connecting 8 memory cells with a single sub-plate line is disclosed, for example, in "A 256 kb Nonvolatile Ferroelectric Memory at 3 V and 100 ns," ISSCC Dig. Tech. pp. 268-229, 1994, authored by T Sumi, N. Moriwaki, et al. However, this structure increases the region of the cell array, having a slower speed than DRAM. Furthermore, it has a low read durability caused by polarization switching during read operation, which is different from other memory devices.
A shadow RAM architecture is a different architecture relating to ferroelectric memories. Such an architecture may overcome the previous problems connected with the pulsed-plate ferroelectric memory. The shadow RAM has two operational modes, which are a ferroelectric memory mode (or ferro-mode, for short) and a DRAM-mode. In the ferro-mode, divided plate lines are fixed at a source voltage V.sub.cc, and the stored voltage is detected as in a DRAM. If it is necessary to securely store information as nonvolatile information, however, the shadow RAM is operated in ferro-mode, or otherwise, in the DRAM-mode. The stored voltage is either 0 V or V.sub.cc, and the plate voltage is V.sub.cc, so that polarization switching does not occur during write and read operations in the DRAM-mode. The resulting unipolar operation provides for a high write/read durability compared to a conventional DRAM.
The high-speed and low-power operation may be achieved in a DRAM-mode because of the fixed voltage of the plate lines. However, since the plate is divided into pulsed plate lines in the ferro-mode, the density may not be improved.
Even though the shadow RAM architecture overcomes the problems of the pulsed-plate ferroelectric memory as previously stated, other problems occur. A refreshing operation to convert the stored volatile information into the nonvolatile information stored in polarization is required prior to power-off, and the reliability of an unexpected power-off is lower than that of the pulsed-plate ferroelectric memory. The refreshing operation is required because the polarity of the ferroelectric capacitor is in the same direction in the DRAM-mode regardless of the stored voltage.
One of the other problems inherent in the shadow RAM architecture is that this architecture can be difficult to use because of the mode switching. In addition, the shadow RAM is incompatible with other types of memories including DRAMs and SRAMs, since additional pins are required to demand the mode switching.
In order to eliminate such problems connected with the pulsed-plate ferroelectric memory and shadow RAM, a non-volatile DRAM device of another architecture is disclosed in IEICE TRANS. ELECTRON, VOL. E79-C. No. 2, February, 1996, entitled "Half-Vcc Plate Nonvolatile DRAMs with Ferroelectric Capacitors," authored by K. Takeuchi, et al.
FIG. 1 shows a conventional half-V.sub.cc plate nonvolatile DRAM. The structure of the memory cell array 10 is essentially the same as that of a conventional DRAM except for the existence of a precharge circuit 14 for selectively supplying one of two precharge voltages, 0 V and V.sub.cc /2 to the bit lines BL.sub.1 and BL.sub.0 according to the operational mode (i.e., ferro-mode or DRAM-mode). For example, the precharge voltage is 0 V in the ferro-mode where polarization is detected, or V.sub.cc /2 in the DRAM-mode. The voltage of the common plate (the PL) is fixed at V.sub.cc /2 in the ferro- and DRAM-mode. Even though such an operational procedure may be applied to the 1T/1C cell structure consisting of one transistor and one ferroelectric capacitor, the conventional memory cell 12 comprises two transistors T.sub.1 and T.sub.2 and two ferroelectric capacitors C.sub.F1 and C.sub.F2.
Unfortunately, the 1T/1C cell structure may not be practically applied because it is difficult to develop the circuits for generating reference voltages to the complementary bit lines. The DRAM further comprises a precharge circuit 14 composed of three connected NMOS transistors M.sub.1, M.sub.2, M.sub.3, sense amplifier 16, and a column pass gate circuit (Y-pass gate circuit) 18 composed of switches M.sub.4 and M.sub.5 respectively connected to the input/output (I/O) lines.
Referring to FIGS. 2A to 2C, the fundamental operation of the memory cell 12 comprises a recall operation, a read/write operation, and a power-off operation. FIG. 2A illustrates the recall operation; FIG. 2B illustrates the read/write operation; and FIG. 2C illustrates the power-off operation.
When power is on, there are detected polarization states induced in the ferroelectric capacitors C.sub.F1 and C.sub.F2 in the recall operation (ferro-mode). At the first recall step, the common plate PL is set to a voltage of V.sub.cc /2 in order to prepare for the recall operation. This is carried out by increasing the voltages of the storage nodes SN.sub.1 and SN.sub.0 in the floating state without losing nonvolatile information. In this case, the word lines WL remain in an inactive state.
At the second recall step, the nonvolatile information (polarized state) is converted into the corresponding volatile information (stored voltage), and an operation similar to the refresh operation of DRAM is carried out until the bit lines BL.sub.1 and BL.sub.0 are precharged with 0 V. The bit line voltage after the activation of the word line is principally determined by the capacitance ratio, depending upon the polarized state of the capacitor as follows.
The bit line voltage after the activation of the word line is kept near 0 V if the capacitance of the bit line is much greater than that of the ferroelectric capacitor. This is caused by the fact that the bit line voltage is 0 V before the activation of the word line while the storage voltage is about V.sub.cc /2. Because the voltage of the common plate PL is V.sub.cc /2, the polarized states of the capacitors take the same direction after the activation of the word line.
As for the 2T/2C cell, the polarized states of the two capacitors are set oppositely. This means that one of the two polarized states is switched after the activation of the word line. The effective capacitance of the switched capacitor is larger than that of the non-switched capacitor since additional charge flows into the switched capacitor. Consequently, the voltage of the bit line BL after the activation of the word line, as shown in FIGS. 2A and 2B, is larger for the bit line BL.sub.1 connected with the switched capacitor than for the bit line BL.sub.0 connected with the non-switched capacitor.
The voltage difference between the bit line pair is detected and amplified by the sense amplifier 16. Then, the word line is non-activated, completing the recall operation respecting the word line. Thus, the recall operation is repeated for all of the word lines connected with the memory cells 12 containing non-volatile information recalled.
After completing the recall operation, the memory cells 12 function in the same way as a DRAM. In read/write operation, the stored voltages are detected by precharging the bit lines BL1 and BL0 with V.sub.cc /2 in (DRAM-mode). The voltage of the PL is fixed at V.sub.cc /2. It should be noted that the polarization is not switched during read operation regardless of the polarized states, which is different from operation in a pulsed-plate ferroelectric memory. The refresh operation is performed in a DRAM-mode as it would be in a conventional DRAM. The polarization switching does not occur in the refresh operation as in the read operation.
When power is on, a restoring operation from volatile information to non-volatile operation is not required, which is different from the operation of a shadow RAM. This is caused by the fact that the non-volatile information (polarized states) is generated simultaneously with the volatile information (stored information), even though the information stored in the conventional memory is changed in DRAM mode during the read operation. The word lines are not activated in order to prevent any loss of information during a power-off operation. In order to securely store information, the voltage of the PL is reduced from V.sub.cc /2 to 0 V during power-off. This prevents the voltage of the storage node SN1 from being lowered faster than the voltage of the PL due to current leakage after stopping the refresh operation.
As described above, the problem with a conventional nonvolatile DRAM is that the detection of polarization, namely, the recall operation, is performed for all the memory cells in the ferro-mode prior to a read/write operation. In addition, since the voltage stored in the storage node may be dissipated at the time in the recall operation, the refresh operation should be performed as in DRAM.